VCO · Phase detector · Loop filter · Lock range · Jitter
A PLL is a feedback control system that makes one oscillator lock its phase and frequency to another. From FM radio demodulators to CPU clock generators, PLLs are one of the most widely used circuits in electronics.
A 2nd-order PLL has three blocks: (1) a Phase Detector that produces a voltage proportional to the phase difference between input and VCO, (2) a Loop Filter that shapes the feedback — a PI (proportional-integral) filter gives zero steady-state phase error, (3) a VCO whose frequency shifts proportionally to its input voltage. The loop dynamics are governed by two parameters: natural frequency ωn (how fast it locks) and damping ratio ζ (how oscillatory the transient is). For ζ = 0.707 (critically damped) the loop settles quickly without ringing. For ζ < 0.5 the phase error overshoots and rings before settling.
Start with the default settings and watch the phase error converge to zero — the PLL acquires lock. Increase the input noise slider and observe how jitter increases. Set ζ to 0.2 (underdamped) and watch the oscillatory acquisition with ringing. Try a large initial phase offset (π) and a small loop bandwidth — the acquisition takes longer. Switch from 1st-order to PI filter to see how the PI eliminates steady-state frequency offset (integral action). The Bode plot updates live to reflect the filter shape.
Every modern processor uses a PLL to multiply a low-frequency reference clock (e.g. 100 MHz crystal) up to GHz speeds (3–5 GHz). GPS receivers use a PLL to lock onto each satellite carrier (1575.42 MHz for L1). The invention of the PLL is credited to Henri de Bellescize, who described it in a 1932 French paper on homodyne reception. The PLL in the original Apollo guidance computer locked to 2048 Hz pulses from an inertial gyroscope.