How the Transistor Changed Everything: From Vacuum Tubes to 2 nm

There are approximately 10²³ transistors on planet Earth — more than there are stars in the observable universe. Since the first point-contact transistor in 1947, every 18–24 months they've halved in size, doubled in count, and halved in cost per operation. Here's how this happened and why it's about to stop.

1. Before Transistors: Vacuum Tubes

The first electronic computers (ENIAC, 1945) used vacuum tubes — glass cylinders from which air was evacuated so heated filaments could emit electrons. A controlling grid electrode modulated the electron flow between cathode and plate, acting as an amplifier or switch.

ENIAC: 18,000 vacuum tubes, 150 kW power, one tube failed every 2 days
Size: each tube ≈ 10 cm tall — a logic gate the size of your fist
Slow: tubes needed warm-up time and burned out frequently
Expensive: one tube cost $10–$35 (1945 dollars)

The computer industry needed something smaller, cooler, more reliable, and cheaper. Bell Labs responded.

2. The 1947 Invention

December 23, 1947 — Bell Labs, Murray Hill NJ

John Bardeen and Walter Brattain demonstrate the first point-contact transistor using two gold-foil contacts pressed onto a germanium crystal. William Shockley leads the team. Nobel Prize in Physics awarded 1956.

1951 — Junction Transistor

Shockley's bipolar junction transistor (BJT) is more reproducible. Texas Instruments and other companies begin manufacturing. Hearing aids become the first mass-market use.

1954 — Silicon Replaces Germanium

Silicon's higher melting point and availability make it preferable. Gordon Teal (TI) produces first silicon transistors. The "Silicon Valley" era begins.

1960 — MOSFET Invented

Dawon Kahng and Martin Atalla (Bell Labs) demonstrate the Metal-Oxide-Semiconductor Field-Effect Transistor. The MOSFET becomes the dominant transistor type by 1980 and remains so today.

3. How a MOSFET Works

A MOSFET has three terminals: Gate, Source, Drain. The silicon substrate between source and drain is doped with the opposite carrier type (n-type or p-type). With no gate voltage, no current flows — the transistor is OFF.

When a voltage exceeds the threshold V_T is applied to the gate, it attracts minority carriers and creates an inversion channel between source and drain. Current flows — the transistor is ON. The gate is insulated from the channel by a thin oxide (SiO₂ historically, now HfO₂ at <1 nm).

I_D (linear) = μ_n\cdotC_ox\cdot(W/L)\cdot[(V_GS - V_T)\cdotV_DS - V_DS²/2] I_D (saturation) = ½\cdotμ_n\cdotC_ox\cdot(W/L)\cdot(V_GS - V_T)² W/L = width-to-length ratio of the channel C_ox = gate oxide capacitance per unit area

The channel length L is what foundries advertise as the "process node" — in 2025, TSMC's 2 nm N2 process has effective gate lengths around 12 nm (the marketing number is complicated by 3D geometry).

4. The Integrated Circuit Revolution

In 1958, Jack Kilby (TI) and Robert Noyce (Fairchild) independently invented the integrated circuit (IC) — multiple transistors and their connections fabricated on a single semiconductor die. Before this, circuits required wiring individual components by hand.

1958: Kilby's first IC — 1 transistor, 3 resistors on germanium. Nobel Prize to Kilby in 2000.
1971: Intel 4004 — 2,300 transistors, 10 µm, first microprocessor
1979: Intel 8088 — 29,000 transistors, 3 µm (IBM PC)
1993: Intel Pentium — 3.1 million transistors, 0.8 µm
2006: Intel Core 2 Duo — 291 million, 65 nm
2020: Apple M1 — 16 billion, 5 nm
2023: Apple M3 Max — 92 billion, 3 nm

5. Moore's Law: 60 Years of Doubling

In 1965, Gordon Moore (co-founder of Intel) observed that the number of transistors on a chip doubled roughly every year (revised to every two years in 1975). This "law" became a self-fulfilling prophecy that organised the entire semiconductor industry.

Transistor count \approx 2^((year - 1971) / 2) Performance per clock cycle improved ~35%/year 1985-2003 Power consumption per transistor fell ~50% per generation Cost per transistor: 1971 = $1.00 ; 2023 = ~$0.000 000 001

Moore's Law is fundamentally an economic and organisational observation, not a law of physics. It requires massive capital investment: a leading-edge fab (TSMC's N2) costs $20–30 billion to build.

6. FinFETs & 3D Transistors

By the 22 nm node (Intel, 2011), planar MOSFETs faced a crisis: leakage current when OFF became too large, wasting power. The solution was the FinFET — a fin-shaped channel protruding vertically from the substrate, with the gate wrapping around three sides. This drastically improves gate control.

At 3 nm (2022) and 2 nm (2025), Intel and TSMC transitioned to Gate-All-Around (GAA) transistors: nanosheet ribbons of silicon with the gate completely surrounding the channel on all four sides. Intel calls this "RibbonFET"; TSMC calls it "NSFET". Maximum possible electrostatic control.

Numbers vs reality: "2 nm" is a marketing designation, not a literal measurement. The actual gate length in an N2 transistor is ~12–15 nm. Node names lost their dimensional meaning around the 20 nm generation; they now represent a competitive performance tier.

7. Physical Limits & What Comes Next

Dennard scaling — the rule that shrinking transistors maintained constant power density — broke down around 2005 due to leakage currents. Clock frequencies stalled at 3–5 GHz around 2004. The industry pivoted to multi-core processors instead of faster single cores.

By the 1 nm node (expected ~2027), transistor channels will be only a few silicon atoms thick. Fundamental limits include:

Quantum tunnelling: At <5 nm channel length, electrons tunnel through the gate barrier even when the transistor should be OFF — causing leakage current that cannot be eliminated
Atomic variability: Random dopant atoms change device properties unpredictably when only ~10 atoms are in the channel
Heat density: Power dissipation per unit area exceeds what cooling can remove

Future directions: 3D-stacked chips (vertical integration), backside power delivery, photonic interconnects, carbon nanotube transistors, 2D semiconductor materials (MoS₂, WS₂), and ultimately quantum computing for specific workloads.